An analysis of on-chip interconnection networks for large-scale chip multiprocessors
نویسندگان
چکیده
منابع مشابه
Distance Analysis for Large - Scale Chip Multiprocessors
Title of dissertation: REUSE DISTANCE ANALYSIS FOR LARGE-SCALE CHIP MULTIPROCESSORS Meng-Ju Wu, Doctor of Philosophy, 2012 Dissertation directed by: Professor Donald Yeung Department of Electrical and Computer Engineering Multicore Reuse Distance (RD) analysis is a powerful tool that can potentially provide a parallel program’s detailed memory behavior. Concurrent Reuse Distance (CRD) and Priva...
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Parallel architectures, such as single-chip multiprocessors (CMPs), have emerged to address power consumption and performance scaling issues in current and future VLSI process technology. Networks-on-chip (NoCs), have concurrently emerged to serve as a scalable alternative to traditional, bus-based interconnection between processor cores. Conventional NoCs in CMPs use wide, point-to-point elect...
متن کامل1 on - Chip Interconnection Networks
My main research is on asynchronous and mixed-timing digital design. Asynchronous circuits have no centralized or global clock. Instead, they are distributed hardware systems where multiple components coordinate and synchronize at their own rate on communication channels. As chips grow increasing larger and faster, power and design-time requirements become more aggressive, and timing variabilit...
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Nowadays, there is a clear trend in industry towards employing the growing amount of transistors on chip in replicating execution cores, where each core is Simultaneous Multithreading (SMT). In order to appropriately connect such a growing number of on-chip execution cores to a shared cache subsystem, some traditional considerations regarding SMT should be re-
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Due to power constraints, computer architects will exploit TLP instead of ILP for future performance gains. Today, 4–8 state-of-the-art cores or 10s of smaller cores can fit on a single die. For the foreseeable future, the number of cores will likely double with each successive processor generation. Hence, CMPs with 100s of cores–so-called large-scale chip multiprocessors (LCMPs)–will become a ...
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ژورنال
عنوان ژورنال: ACM Transactions on Architecture and Code Optimization
سال: 2010
ISSN: 1544-3566,1544-3973
DOI: 10.1145/1736065.1736069